1. C. Hu, Low-voltage CMOS device scaling, in: ISSCC Technical Papers, February 1994, pp. 86–87.
2. CMOS scaling in the 0.1-μm 1.X volt regime for high performance applications;Shahidi et al;IBM J. Res. Dev.,1995
3. Duvvury et al., ESD design for deep submicron SOI technology, in: Proc. Symp. on VLSI Technology Digest of Technical Papers, 1996, pp. 194–195.
4. J.C. Smith, M. Lien, S. Veeraraghavan, ESD protection circuits for TFSOI technology, in: Proc. 1996 IEEE Int. SOI Conf., 1996, pp. 170–171.
5. S. Voldman et al., CMOS-on-SOI ESD protection networks, in: EOS/ESD Symp. Proc., September 1996, pp. 291–301.