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Distributed topology discovery in self-assembled nano network-on-chip

  • Published:2014-11 Issue:8 Volume:40 Page:292-306
  • ISSN:0045-7906
  • Container-title:Computers & Electrical Engineering
  • language:en
  • Short-container-title:Computers & Electrical Engineering

Author:

Catania Vincenzo,Mineo Andrea,Monteleone Salvatore,Patti Davide

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering

Reference26 articles.

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2. A comparative analysis of performance improvement schemes for cache memories;Kavi;Comput Electr Eng,2012

3. Design and evaluation of low latency interconnection networks for real-time many-core embedded systems;Sibai;Comput Electr Eng,2011

4. Dna-templated self-assembly of protein arrays and highly conductive nanowires;Yan;Science,2003

5. Nana: a nano-scale active network architecture;Patwardhan;J Emerg Technol Comput Syst,2006

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1. Packetization of Shared-Memory Traces for Message Passing Oriented NoC Simulation;Lecture Notes in Computer Science;2018

2. Packet routing in 3D nanonetworks: A lightweight, linear-path scheme;Nano Communication Networks;2017-06

3. Cycle-Accurate Network on Chip Simulation with Noxim;ACM Transactions on Modeling and Computer Simulation;2016-11-18

4. Stateless Linear-path Routing for 3D Nanonetworks;Proceedings of the 3rd ACM International Conference on Nanoscale Computing and Communication;2016-09-28

5. Lightweight, self-tuning data dissemination for dense nanonetworks;Nano Communication Networks;2016-06
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