Author:
Catania Vincenzo,Salvatore Monteleone,Palesi Maurizio,Patti Davide
Publisher
Springer International Publishing
Reference26 articles.
1. Agarwal, N., Krishna, T., Peh, L.S., Jha, N.K.: Garnet: a detailed on-chip network model inside a full-system simulator. In: IEEE International Symposium on Performance Analysis of Systems and Software, 2009, ISPASS 2009, pp. 33–42. IEEE (2009)
2. Ascia, G., Catania, V., Di Nuovo, A.G., Palesi, M., Patti, D.: Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. J. 11(1), 382–398 (2011).
https://doi.org/10.1016/j.asoc.2009.11.029
3. Benini, L., Micheli, G.D.: Networks on chips: a new SoC paradigm. IEEE Comput. 35(1), 70–78 (2002)
4. Bienia, C., Li, K.: PARSEC 2.0: a new benchmark suite for chip-multiprocessors. In: Proceedings of the 5th Annual Workshop on Modeling, Benchmarking and Simulation, June 2009
5. Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M.D., Wood, D.A.: The gem5 simulator. SIGARCH Comput. Archit. News 39(2), 1–7 (2011).
https://doi.org/10.1145/2024716.2024718
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Exploiting Data Resilience in Wireless Network-on-chip Architectures;ACM Journal on Emerging Technologies in Computing Systems;2020-04-30
2. 3D-ReG;ACM Journal on Emerging Technologies in Computing Systems;2020-04-30