Author:
Kavi Krishna,Nwachukwu Izuchukwu,Fawibe Ademola
Subject
Electrical and Electronic Engineering,General Computer Science,Control and Systems Engineering
Reference22 articles.
1. Givargis T. Improved indexing for cache miss reduction in embedded systems. In: IEEE/ACM design automation conference (DAC). Anaheim; 2003. p. 872–80.
2. Naz A, Adamo O, Kavi K, Janjusic T. Improving uniformity of cache access patterns using split data caches. In: Proceedings of ISCA conference on parallel and distributed computer systems (PDCS-2009). KY: Louisville; 2009.
3. Peir J, Lee Y, Hsu W. Capturing dynamic memory reference behavior with adaptive cache topology. In: Proceedings of the 8th international conference on architectural support for programming language and operating systems (TOPLAS); 1998. p. 240–50.
4. Zhang C. Balanced cache: reducing conflict misses of direct-mapped caches. In: ACM international symposium on computer architecture (ISCA-06); 2006. p. 155–66.
5. Adamo O, Naz A, Kavi K, Janjusic T, Chung CP. Smaller split L-1 data caches for multi-core processing systems. Proceedings of IEEE 10th international symposium on pervasive systems, algorithms and networks (I-SPAN 2009). Taiwan: Kao-Hsiung; 2009. p. 14–6.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献