Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors-Reference-Cited by-同舟云学术

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Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

Published:2013-08 Issue:6 Volume:13 Page:1143-1149
ISSN:1567-1739
Container-title:Current Applied Physics
language:en
Short-container-title:Current Applied Physics

Author:

Lee Jae Sung,Seo Jae Hwa,Cho Seongjae,Lee Jung-Hee,Kang Shin-Won,Bae Jin-Hyuk,Cho Eou-Sik,Kang In Man

Publisher

Elsevier BV

Subject

General Physics and Astronomy,General Materials Science

Reference25 articles.

1. Low-subthreshold-swing tunnel transistors

2. Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec

3. Band-to-Band Tunneling in Carbon Nanotube Field-Effect Transistors

4. Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions

5. P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths

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2. Analysis on performances of ultra-thin vertical MOSFET depending on position of gate–drain misalignment;Japanese Journal of Applied Physics;2024-05-01

3. A Review on Emerging Tunnel FET Structures for High-speed and Low-power Circuit Applications;2023 IEEE Devices for Integrated Circuit (DevIC);2023-04-07

4. Performance analysis of dielectric modulated underlap FD-SOI MOSFET for biomolecules detection;Applied Physics A;2022-11-22

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