Modeling of hole confinement gate voltage range for SiGe channel p-MOSFETs
Author:
Publisher
Elsevier BV
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference17 articles.
1. Enhancement-mode quantum-well Ge/sub x/Si/sub 1-x /PMOS
2. Hole confinement MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructures
3. A gate-quality dielectric system for SiGe metal-oxide-semiconductor devices
4. Hole mobility enhancement in MOS-gated Ge/sub x/Si/sub 1-x//Si heterostructure inversion layers
5. High-mobility modulation-doped SiGe-channel p-MOSFETs
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1. Application of stratified implantation for silicon micro-strip detectors;Chinese Physics C;2015-06
2. Design and optimization of a buried channel PMOS integrable in a Si1−xGex BiCMOS process;Solid-State Electronics;2007-06
3. Multilayer protection analysis for photovoltaic manufacturing facilities;Process Safety Progress;2001-06
4. Influence of technological parameters on the behavior of the hole effective mass in SiGe structures;Journal of Applied Physics;2000-08-15
5. Hole confinement and low-frequency noise in SiGe pFETs on silicon-on-sapphire;IEEE Electron Device Letters;1999-04
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