Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate-Reference-Cited by-同舟云学术

Effect of Si interlayer thickness and post-metallization annealing on Ge MOS capacitor on Ge-on-Si substrate

Published:2008-12 Issue: Volume:154-155 Page:102-105
ISSN:0921-5107
Container-title:Materials Science and Engineering: B
language:en
Short-container-title:Materials Science and Engineering: B

Author:

Yoo Ook Sang,Oh Jungwoo,Kang Chang Yong,Lee Byoung Hun,Han In Shik,Choi Won-Ho,Kwon Hyuk-Min,Na Min-Ki,Majhi Prashant,Tseng Hsing-Huang,Jammy Raj,Wang Jin Suk,Lee Hi-Deok

Publisher

Elsevier BV

Subject

Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science

Reference11 articles.

1. Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

2. Low defect ultra-thin fully strained-Ge MOSFET on relaxed Si with high mobility and low band-to-band-tunneling (BTBT)

3. Interface characteristics of ZrO2 high-k gate dielectrics on epitaxial Ge capacitor layers after thermal desorption of Ge native oxide and Ge nitridation

4. Threshold voltage shifts in Si passivated (100)Ge p-channel field effect transistors: Insights from first-principles modeling

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