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Formal reliability analysis of combinational circuits using theorem proving

  • Published:2011-03 Issue:1 Volume:9 Page:41-60
  • ISSN:1570-8683
  • Container-title:Journal of Applied Logic
  • language:en
  • Short-container-title:Journal of Applied Logic

Author:

Hasan Osman,Patel Jigar,Tahar Sofiène

Publisher

Elsevier BV

Subject

Applied Mathematics,Logic

Reference25 articles.

1. Model checking algorithms for continuous time Markov chains;Baier;IEEE Transactions on Software Engineering,2003

2. Systems and Software Verification: Model-Checking Techniques and Tools;Berard,2001

3. NANOPRISM: A tool for evaluating granularity versus reliability trade-offs in nano architectures;Bhaduri,2004

4. Scalable techniques and tools for reliability analysis of large circuits;Bhaduri;IEEE Trans. Circuits and Systems,2007

5. A formulation of the simple theory of types;Church;Journal of Symbolic Logic,1940

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1. Formal verification of a 4 bit counter using Kami verification flow;RECENT TRENDS IN SCIENCE AND ENGINEERING;2022

2. CoCEC: An Automatic Combinational Circuit Equivalence Checker Based on the Interactive Theorem Prover;Complexity;2021-05-25

3. Formal Verification of Hardware Components in Critical Systems;Wireless Communications and Mobile Computing;2020-02-20

4. Formal Probabilistic Analysis of Low Latency Approximate Adders;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2019-01

5. Formal Dependability Modeling and Analysis: A Survey;Lecture Notes in Computer Science;2016
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