Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware-Reference-Cited by-同舟云学术

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Efficient dynamic priority based soft error mitigation techniques for configuration memory of FPGA hardware

Published:2017-06 Issue: Volume:51 Page:313-330
ISSN:0141-9331
Container-title:Microprocessors and Microsystems
language:en
Short-container-title:Microprocessors and Microsystems

Author:

Mandal Swagata,Paul Rourab,Sau Suman,Chakrabarti Amlan,Chattopadhyay Subhasis

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference46 articles.

1. Single event upset mitigation techniques for programmable devices;de Lima;Porto Alegre,2000

2. A systematic approach to ser estimation and solutions;Nguyen,2003

3. Soft error mitigation for sram-based fpgas;Asadi,2005

4. Single-event-upset (seu) awareness in fpga routing;Golshan,2007

5. Simulation-based analysis of seu effects in sram-based fpgas;Violante;Nuclear Sci., IEEE Trans.,2004

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4. Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique;2019 19th European Conference on Radiation and Its Effects on Components and Systems (RADECS);2019-09

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