Configuration Memory Scrubbing of the Xilinx Zynq-7000 FPGA using a Mixed 2-D Coding Technique

Author:

Vlagkoulis Vasileios1,Sari Aitzan1,Proko Juljan1,Zografakis Dimitrios1,Psarakis Mihalis1,Tavoularis Antonios1,Furano Gianluca2,Boatella-Polo Cesar2,Poivey Christian2,Ferlet-Cavrois Veronique2,Kastriotou Maria3,Martinez Pablo Fernandez3,Alia Ruben Garcia3

Affiliation:

1. University of Piraeus,Department of Informatics,Greece

2. European Space Agency, ESTEC,Noordwijk,The Netherlands

3. CERN,Geneva,Switzerland

Funder

European Space Agency (ESA)

Publisher

IEEE

Reference12 articles.

1. A hybrid approach to FPGA configuration scrubbing;aaron;IEEE Transactions on Nuclear Science,2017

2. Analysis of the Single Event Upsets in the Programmable Logic of 28 nm Xilinx Zynq-7000 FPGA due to Heavy Ion Irradiation;vlagkoulis;Single Event Effects (SEE) Symposium and Military and Aerospace Programmable Logic Devices (MAPLD) Workshop,0

3. A bit-interleaved embedded hamming scheme to correct single-bit and multi-bit upsets for SRAM-based FPGAs;shyamsundar;2014 24th International Conference on Field Programmable Logic and Applications (FPL) FPL,0

4. An Open-source Framework for Xilinx FPGA Reliability Evaluation;sari;Workshop on Open Source Design Automation (OSDA),0

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