Genetic Algorithm-based Reliability Optimization for High-Level Synthesis

Abstract

Soft errors (SEs) are a type of transient errors in integrated circuits (ICs) caused by radiation effects in the chips. They have become the major concern in IC design process in each CMOS technology generation since the decrease in supply voltage levels for shrinking transistor sizes makes the circuits more vulnerable than before. Previous studies generally use hardware redundancy for combinational circuits and error correcting codes for memory elements to mitigate or eliminate the SEs. However, adding extra hardware in final design may not always be possible if the design has tight area constraints. Different implementations of the same function may have different soft error rates (SERs) due to their error masking capabilities. Therefore, we can obtain various versions of the same function with different area, latency, and reliability values. Allocating the best resources to the operations of the design under area and latency constraints to optimize the overall system reliability has NP-complete time complexity. Evolutionary computing-based methods suit very well for this optimization problem. Motivated by this fact, in this paper, we present a genetic algorithm (GA)-based design method to increase the reliability of application-specific integrated circuits (ASICs). In this method, we use different versions of the same resources, each having a different area, latency, and reliability values. The goal of the GA-based optimizer is to allocate the best available resources to the application nodes to maximize the reliability of the design under tight area and latency constraints. Our experimental results show that we achieve up to 20.86% reliability improvement against a heuristic method with no additional area overhead. In order to further increase the reliability of the final design, we also propose a heuristic-based post-processing method, which adds duplicate resources to the final design without violating the constraint.