An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip

Author:

Safaei Farshad,ValadBeigi Majed

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software

Reference35 articles.

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5. Y. Taur, et al., CMOS scaling into the nanometer regime, in: Proceedings of the IEEE, vol. 85, April 1997.

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