Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services-Reference-Cited by-同舟云学术

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Bio-inspired NoC fault tolerant techniques using guaranteed throughput and best effort services

Published:2016-06 Issue: Volume:54 Page:65-96
ISSN:0167-9260
Container-title:Integration
language:en
Short-container-title:Integration

Author:

Sethi Muhammad Athar Javed,Hussin Fawnizu Azmadi,Hamid Nor Hisham

Funder

Universiti Teknologi PETRONAS

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference138 articles.

1. Network-on-Chip design and synthesis outlook;Atienza;Integr. VLSI J.,2008

2. A networks-on-chip architecture design space exploration–the LIB;Liu;Comput. Electr. Eng.,2009

3. An efficient routing methodology to tolerate static and dynamic faults in 2-D mesh networks-on-chip;Safaei;Microprocess. Microsyst.,2012

4. Clustered NOC, a suitable design for group communications in network on Chip;Seifi;Comput. Electr. Eng.,2012

5. Æthereal network on chip: concepts, architectures, and implementations;Goossens;Design Test of Computers, IEEE,2005

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Bio-Inspired Solutions and Its Impact on Real-World Problems: A Network on Chip (NoC) Perspective;Application Specific Integrated Circuits - Technologies, Digital Systems and Design Methodologies;2019-04-17

2. Review of Network on Chip Architectures;Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering);2017-07-07

3. Bio-inspired fault tolerant network on chip;Integration;2017-06

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