1. Semiconductor Industry Association (SIA); Internet: www.semichips.org. International Technology Roadmap for Semiconductors; internet; public.itrs.net: 2003 edition.
2. Application of chemical mechanical polishing to the fabrication of VLSI circuit interconnections;Patrick;J Electrochem Soc,1991
3. Beyer KD, Guthrie WL, Makarewicz SR, Mendel E, Patrick WJ, Perry KA, Pliskin WA, Riseman J, Schiable PM, Standley CL. Chem-mech polishing method for producing coplanar metal/insulator films on a substrate. US Pat 4,944,836 (1990).
4. SEMI standard M43-0301. Guide for reporting wafer nantopography. Semiconductor Equipment and Materials International (SEMI), Milpitas, CA, USA, 2001. Internet: www.semi.org.
5. Kishimoto J. Semiconductor wafer and method for fabrication thereof. Europ Pat EP 1 005 069 A2 (2000).