Error Generation for 3D NAND Flash Memory
Author:
Affiliation:
1. Wuhan National Laboratory for Optoelectronics, Key Laboratory of Information Storage System, Engineering Research Center of Data Storage Systems and Technology,Ministry of Education of China
Funder
National Natural Science Foundation of China
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774514.pdf?arnumber=9774514
Reference12 articles.
1. A 1 tb 4bcell 5th-generation 3d-nand flash memory with 2ms tprog, 110us tr and 1. 2 gbspin interface;kim;2021 IEEE International Memory Workshop (IMW),0
2. 3-D NAND Technology Achievements and Future Scaling Perspectives
3. Reliability of Solid-State Drives Based on NAND Flash Memory
4. Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory
5. Characterizing the Reliability and Threshold Voltage Shifting of 3D Charge Trap NAND Flash
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2. LDPC Level Prediction Toward Read Performance of High-Density Flash Memories;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2023-10
3. Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics;ACM Transactions on Design Automation of Electronic Systems;2023-04-18
4. Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative Nets;2023 Design, Automation & Test in Europe Conference & Exhibition (DATE);2023-04
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