Towards LDPC Read Performance of 3D Flash Memories with Layer-induced Error Characteristics

Author:

Du Yajuan1ORCID,Huang Siyi1ORCID,Zhou Yao1ORCID,Li Qiao2ORCID

Affiliation:

1. Wuhan University of Technology, Gongda Road, Hongshan District, Wuhan, Hubei Province

2. Xiamen University, Siming District, Xiamen

Abstract

3D flash memories have been widely developed to further increase the storage capacity of SSDs by vertically stacking multiple layers. However, this special physical structure brings new error characteristics. Existing studies have discovered that there exist significant Raw Bit Error Rate (RBER) variations among different layers and RBER similarity inside the same layer due to the manufacturing process. These error characteristics would introduce a new data reliability issue. Currently, Low-Density Parity-Check (LDPC) code has been widely used to ensure the data reliability of flash memories. It can provide stronger error correction capability for high RBERs by trading with longer read latency. Traditional LDPC codes designed for planar flash memories do not consider the layer RBER characteristics of 3D flash memories, which may induce sub-optimal read performance. This article first investigates the effect of RBER characteristics of 3D flash memories on read performance and then obtains two observations. On one hand, we observe that LDPC read latencies are largely diverse in different flash layers and increase in diverse speeds along with data retention. This phenomenon is caused by the inter-layer RBER variation. On the other hand, we also compare RBERs between different pages of the same flash layer and observe that read latencies with LDPC codes are quite similar, which is caused by the intra-layer RBER similarity. Then, by exploiting these two observation results, this article proposes a Multi-Granularity LDPC (MG-LDPC) read method to adapt read latency increase characteristics across 3D flash layers. In detail, we design five LDPC decoding engines with varied read level increase granularity (higher level induces higher latency) and assign these engines to each layer dynamically according to prior information, or in a fixed way. A series of experimental results demonstrate that the fixed and dynamic MG-LDPC methods can reduce SSD read response time by 21% and 51% on average, respectively.

Funder

Shenzhen Fundamental Research Program

National Natural Science Foundation of China

Publisher

Association for Computing Machinery (ACM)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Computer Science Applications

Reference59 articles.

1. Open NAND Flash Specification. (n. d.). Retrieved November 2016 from http://www.onfi.org/specifications.

2. N. Agrawal, V. Prabhakaran, T. Wobber, J. D. Davis, M. S. Manasse, and R. Panigrahy. 2008. Design tradeoffs for SSD performance. In USENIX Annual Technical Conference. 57–70.

3. BCH and LDPC Error Correction Codes for NAND Flash Memories

4. J. Bucy J. Schindler S. Schlosser and G. Ganger. 2008. The DiskSim Simulation Environment (v4.0). Retrieved November 2016 from http://www.pdl.cmu.edu/DiskSim/.

5. Error characterization, mitigation, and recovery in flash-memory-based solid-state drives;Cai Y.;Proc. IEEE,2017

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3. PEAR: Unbalanced Inter-Page Errors Aware Read Scheme for Latency-Efficient 3D NAND Flash;IEEE Transactions on Device and Materials Reliability;2023

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