Gate length dependence of hot carrier injection degradation in short channel silicon on insulator planar MOSFET

Abstract

With the continued device scaling and the introduction of new device structures, MOSFET reliability phenomena arising from the hot carrier injection (HCI) stress have received extensive attention from both the academia and the industry community. In this work, the degradations of ultra-scaled silicon on insulator (SOI) MOSFETs under the HCI stress are investigated on devices of different gate lengths (L=30-150 nm). Our experimental data demonstrate that the time evolutions of the threshold voltage change (Vth) under the HCI stress for different gate length devices are the same, and the magnitude of Vth reduces for the shorter devices. The degradation of the device under the HCI stress should be due to both the channel hot carrier (CHC) effect and the bias temperature instability (BTI) effect. The distribution and magnitude of the electric field along the MOSFET's channel are analyzed. It is confirmed that besides the well-known CHC effect in the depletion region close to the drain side, a strong BTI effect co-exists in the channel close to the source side. This degradation mechanism is different from the conventional HCI stress. With the gate length decreasing, the contribution of the aforementioned BTI effect becomes larger, and it dominates in the degradation. One feature of the BTI effects is that the corresponding degradation is small when the gate length is short. This is consistent with our experimental result that the change of Vth is small for the device of short gate length under the accelerated HCI stress. The time evolution of Vth can be described by the equation Vth=A•tn, where A is a constant, t is the stress time, and n is the power law exponent obtained by the curve fitting. In this study, the power law exponent n of pMOSFET is larger than that of nMOSFET. This experimental fact can lead to the point that the BTI effect exists during the HCI stress because the BTI effect in ultra-scaled pMOSFETs is more significant than that in nMOSFETs. The stress-recover experiments of the HCI stress on MOSFTTs show larger recovery in device of shorter gate length. It is found that the ratio of the recovery to the total degradation in the 30 nm gate-length device is almost twice as large as that in the 150 nm device. The degradation from the CHC effect has no recovery, and the larger recovery in the shorter-channel device implies the larger component of the BTI degradation. Another intriguing fact is that our experimental result on SOI MOSFET is inconsistent with the recently reported result on FinFET. We argue that the reported stronger HCI degradation in FinFET may not be ascribed only to the stronger electric field in the shorter channel, but also to the fact that the FinFET' channel is three-dimensionally surrounded by the gate dielectric. This kind of three-dimensional structure significantly increases the chance for electrons or holes to be injected into the dielectric layer. Therefore the HCI reliability of planar SOI MOSFETs may be better than that of FinFETs at the same level of gate length. In conclusion, the BTI effect is an important source of the degradation during the HCI stress in ultra-short-channel device, and it is no more negligible in analyzing the underlying physical mechanism.