Electrical properties of LaTiO high-k gate dielectric Ge MOS Capacitor and Ti content optimization

Abstract

Ti is intentionally added into La2O3 to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capacitor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La2O3 ratios (10.6%, 18.4%, 25.7% and 31.5%) are deposited by reactively co-sputtering Ti and La2O3 targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La2O3. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La2O3 ratios in the examined range, the largest Ti/La2O3 ratio is 31.5%, which results in the highest k value of 29.4, the largest gate-leakage current of 9.710-2 Acm-2 at Vg=1 V, the highest interface-sate density of 4.51012 eV-1cm-2 and the worst device reliability, while the La2O3 film without Ti incorporation exhibits the lowest k value of 11.7, the smallest gate-leakage current of 2.510-3 Acm-2 at Vg=1 V, the lowest interface-sate density of 3.31011 eV-1cm-2 and the best device reliability. As far as the trade-off among the electrical properties is concerned, 18.4% is the most suitable Ti/La2O3 ratio, which leads to a higher k value of 22.7, lower interface-sate density of 5.51011 eV-1cm-2, an acceptable gate-leakage current of 7.110-3 Acm-2 at Vg=1 V, and a better device reliability. In view of the fact mentioned above, excellent electrical properties could be obtained by setting Ti content to be an optimal value. Therefore, the optimization of Ti content is critical for LaTi-based oxide Ge MOS device preparation.