Investigation of 4H-SiC gate-all-around cylindrical nanowire junctionless MOSFET including negative capacitance and quantum confinements
Author:
Publisher
Springer Science and Business Media LLC
Subject
General Physics and Astronomy
Link
https://link.springer.com/content/pdf/10.1140/epjp/s13360-021-01787-0.pdf
Reference42 articles.
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2. J. Singh, A.K. Jain, M.J. Kumar, Realizing a planar 4H-SiC junctionless FET for sub-10-nm regime using P+ pocket. IEEE Trans. Electron Devices 66(7), 3209–3214 (2019). https://doi.org/10.1109/TED.2019.2914633
3. D. Madadi, A.A. Orouji, A. Abbasi, Improvement of nanoscale SOI MOSFET heating effects by vertical gaussian drain-source doping region. SILICON (2020). https://doi.org/10.1007/s12633-020-00453-x
4. D. Madadi, A.A. Orouji, Investigation of short channel effects in SOI MOSFET with 20 nm channel length by a β-Ga2O3 layer. ECS J. Solid State Sci. Technol. 9(4), 045002 (2020). https://doi.org/10.1149/2162-8777/ab878b
5. D. Il Moon, S.J. Choi, J.P. Duarte, Y.K. Choi, Investigation of silicon nanowire gate-all-around junctionless transistors built on a bulk substrate. IEEE Trans. Electron Devices 60(4), 1355–1360 (2013). https://doi.org/10.1109/TED.2013.2247763
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