Performance improvement of junctionless SOI-MOSFETs by a superior depletion technique

Abstract

Abstract This work uses a superior depletion technique to present a junctionless silicon-on-insulator (SOI) metal-oxide field-effect transistor (MOSFET) in a 14 nm regime. The suggested technique embeds a P-type area into the buried silicon oxide (SiO2) layer. The p-silicon area has several effects on the proposed structure (EPB-JLSM): First, it helps us attain a full depletion area in the channel. Second, the self-heating improves due to the higher thermal conductivity of silicon than the silicon nitride. Finally, the embedded area causes the lower hole concentration (high Vds at accumulation mode), resulting in a better kink effect. Also, we discuss the impact of inserting the P-silicon area geometry into the buried layer on the DC performance device, such as height and thickness. The P-silicon area decreases the leakage current (IOFF) by three orders of magnitude (∼1000%), and also slightly enhances the drive current (ION) (∼20%), and reduces subthreshold swing (SS) from 186 to 109 mV dec−1 (∼71%) compared to a typical junctionless SOI MOSFET (C-JLSM). Furthermore, we discuss the effect of the buried region and gate insulator materials on the proposed device’s performance.