Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket-Reference-Cited by-同舟云学术

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Realizing a Planar 4H-SiC Junctionless FET for Sub-10-nm Regime Using P+ Pocket

Published:2019-07 Issue:7 Volume:66 Page:3209-3214
ISSN:0018-9383
Container-title:IEEE Transactions on Electron Devices
language:
Short-container-title:IEEE Trans. Electron Devices

Author:

Singh Jaspreet^ORCID,Jain Aakash Kumar^ORCID,Kumar Mamidala Jagadesh^ORCID

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

http://xplorestaging.ieee.org/ielx7/16/8736764/08718036.pdf?arnumber=8718036

Cited by 24 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An analytical model of P SiC core-shell JLFETs to analyze the performance for higher breakdown voltages applications;Micro and Nanostructures;2024-07

2. Exploring the Potential of Silicon Carbide Nanowire Junctionless Field-Effect Transistors for Ultra-Scaled 5 nm Channel Length Applications;2024 IEEE 3rd International Conference on Electrical Power and Energy Systems (ICEPES);2024-06-21

3. A temperature dependent drain current model of P+ SiC GAA JLFETs for enhanced analog/RF performance;Micro and Nanostructures;2024-04

4. β-Ga₂O₃ Based Bulk-Planar Junctionless Transistor for Superior Electrostatic Integrity at Sub-7nm Technology;2024 IEEE International Conference on Interdisciplinary Approaches in Technology and Management for Social Innovation (IATMSI);2024-03-14

5. Modeling and Simulation of RRAM With Carbon Nanotube Electrode;IEEE Transactions on Nanotechnology;2024

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