Measurement Results of Real Circuit Delay Degradation under Realistic Workload
Author:
Affiliation:
1. Hitachi, Ltd.
Publisher
Information Processing Society of Japan
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://www.jstage.jst.go.jp/article/ipsjtsldm/16/0/16_27/_pdf
Reference14 articles.
1. [1] Wang, W., Yang, S., Bhardwaj, S., Vrudhula, S., Liu, F. and Cao, Y.: The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis, IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol.18, No.2, pp.173-183 (2010).
2. [2] Kükner, H., Weckx, P., Morrison, S., Raghavan, P., Kaczer, B., Catthoor, F., Van der Perre, L., Lauwereins, R. and Groeseneken, G.: NBTI aging on 32-bit adders in the downscaling planar FET technology nodes, 17th Euromicro Conference on Digital System Design (Aug. 2014).
3. [3] Mintarno, E., Chandra, V., Pietromonaco, D., Aitken, R. and Dutton, R.W.: Workload Dependent NBTI and PBTI Analysis for a sub-45nm Commercial Microprocessor, IEEE International Reliability Physics Symposium (IRPS) (Apr. 2013).
4. [4] Shimamura, K. and Ikeda, N.: Real Circuit Delay Measurement Method by Variable Frequency Operation with On-Chip Fine Resolution Oscillator, IPSJ Trans. System LSI Design Methodology, Vol.13, pp.21-30 (Feb. 2020).
5. [5] Ma, C., Mattausch, H.J., Matsuzawa, K., Yamaguchi, S., Hoshida, T., Imade, M., Koh, R., Arakawa, T. and Miura-Mattausch, M.: Universal NBTI Compact Model for Circuit Aging Simulation under Any Stress Conditions, IEEE Trans. Device and Materials Reliability, Vol.14, No.3, pp.818-825 (Sep. 2014).
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