High-level Synthesis for Low-power Design-Reference-Cited by-同舟云学术

High-level Synthesis for Low-power Design

Published:2015 Issue:0 Volume:8 Page:12-25
ISSN:1882-6687
Container-title:IPSJ Transactions on System LSI Design Methodology
language:en
Short-container-title:IPSJ Transactions on System LSI Design Methodology

Author:

Zhang Zhiru¹,Chen Deming²,Dai Steve¹,Campbell Keith²

Affiliation:

1. School of Electrical and Computer Engineering, Cornell University

2. Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign

Publisher

Information Processing Society of Japan

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://www.jstage.jst.go.jp/article/ipsjtsldm/8/0/8_12/_pdf

Reference103 articles.

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2. [2] Altera: Cyclone V SoCs: Lowest system cost and power, Altera (online), available from <http://www.altera.com/devices/processor/soc-fpga/cyclone-v-soc/cyclone-v-soc.html> (accessed 2014-10-31).

3. [3] Anthony, S.: Intel unveils new Xeon chip with integrated FPGA, touts 20x performance boost, ExtremeTech (online), available from <http://www.extremetech.com/extreme/184828-intel-unveils-new-xeon-chip-with-integrated-fpga-touts-20x-performance-boost> (accessed 2014-10-31).

4. [4] Babighian, P., Benini, L. and Macii, E.: A scalable ODC-based algorithm for RTL insertion of gated clocks, Design, Automation, and Test in Europe (DATE), pp.500-505 (2004).

5. [5] Bastoul, C.: Code generation in the polyhedral model is easier than you think, Int'l Conf. Parallel Architecture and Compilation Techniques (PACT), pp.7-16 (2004).

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