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Spider monkey optimization–based high‐level synthesis in VLSI circuits for runtime adaptability

  • Published:2019-05-09 Issue:3 Volume:33 Page:
  • ISSN:1532-0626
  • Container-title:Concurrency and Computation: Practice and Experience
  • language:en
  • Short-container-title:Concurrency Computat Pract Exper

Author:

Rani M. Thillai1ORCID,Kumar S. Suresh2

Affiliation:

1. Anna University Chennai India

2. Department of Electronics and Communication Engineering Dr. N.G.P. Institute of Technology Coimbatore India

Publisher

Wiley

Subject

Computational Theory and Mathematics,Computer Networks and Communications,Computer Science Applications,Theoretical Computer Science,Software

Reference21 articles.

1. GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis

2. Integrating operation scheduling and binding for functional unit power‐gating in high‐level synthesis;Wang N;Integr VLSI J,2017

3. A High-Level Synthesis Scheduling and Binding Heuristic for FPGA Fault Tolerance

4. Hardware design of a high speed VLSI comparator framework for DNA sequence matching using high level synthesis;Verma S;Int J Adv Technol,2011

5. A High-Level Design Framework for the Automatic Generation of High-Throughput Systolic Binomial-Tree Solvers

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A review of spider monkey optimization: modification and its biomedical application;International Journal on Interactive Design and Manufacturing (IJIDeM);2023-12-22

2. Recurrent deep neural learning classification algorithm based high level synthesis in VLSI circuit with runtime adaptability;Journal of Intelligent & Fuzzy Systems;2022-07-21
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