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High-level synthesis with timing-sensitive information flow enforcement

Published:2018-11-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Conference on Computer-Aided Design
language:
Short-container-title:

Author:

Jiang Zhenghong¹,Dai Steve¹,Suh G. Edward¹,Zhang Zhiru¹

Affiliation:

1. Cornell University

Funder

Semiconductor Research Corporation

National Science Foundation

Defense Advanced Research Projects Agency

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3240765.3243415

Reference41 articles.

1. Transforming out timing leaks

2. Armaiti Ardeshiricham Wei Hu Joshua Marxen and Ryan Kastner. Register Transfer Level Information Flow Tracking for Provably Secure Hardware Design. Design Automation and Test in Europe (DATE) 2017. Armaiti Ardeshiricham Wei Hu Joshua Marxen and Ryan Kastner. Register Transfer Level Information Flow Tracking for Provably Secure Hardware Design. Design Automation and Test in Europe (DATE) 2017.

3. Andrew Canis Stephen D. Brown and Jason H. Anderson. Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis. Int'l Conf. on Field Programmable Logic and Applications (FPL) 2014. Andrew Canis Stephen D. Brown and Jason H. Anderson. Modulo SDC Scheduling with Recurrence Minimization in High-Level Synthesis. Int'l Conf. on Field Programmable Logic and Applications (FPL) 2014.

4. Andrew Canis Jongsok Choi Mark Aldham Victor Zhang Ahmed Kammoona Jason H. Anderson Stephen Brown and Tomasz Czajkowski. LegUp: High-level Synthesis for FPGA-Based Processor/Accelerator Systems. Int'l Symp. on Field-Programmable Gate Arrays (FPGA) 2011. 10.1145/1950413.1950423 Andrew Canis Jongsok Choi Mark Aldham Victor Zhang Ahmed Kammoona Jason H. Anderson Stephen Brown and Tomasz Czajkowski. LegUp: High-level Synthesis for FPGA-Based Processor/Accelerator Systems. Int'l Symp. on Field-Programmable Gate Arrays (FPGA) 2011. 10.1145/1950413.1950423

5. High-Level Synthesis for FPGAs: From Prototyping to Deployment

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1. Iterative Mitigation of Insecure Resource Sharing Produced by High-level Synthesis;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

2. Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

3. Challenges and Opportunities of Security-Aware EDA;ACM Transactions on Embedded Computing Systems;2023-04-19

4. Designing Constant-Timed Accelerators using High-Level Synthesis: A Case Study of ECG Biometric Authentication;2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT);2023-04-17

5. SecHLS;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16

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