Power Reduction Using High-Level Clock-Gating-Reference-Cited by-同舟云学术

登录注册会员服务联系我们

Power Reduction Using High-Level Clock-Gating

Published:2011-09-12 Issue: Volume: Page:119-129
ISSN:
Container-title:Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
language:
Short-container-title:

Author:

Ahuja Sumit,Lakshminarayana Avinash,Shukla Sandeep Kumar

Publisher

Springer New York

Link

http://link.springer.com/content/pdf/10.1007/978-1-4614-0872-7_10.pdf

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. High-level Synthesis for Low-power Design;IPSJ Transactions on System LSI Design Methodology;2015

2. Multi-view Power Modeling Based on UML, MARTE and SysML;2012 38th Euromicro Conference on Software Engineering and Advanced Applications;2012-09

同舟云学术

1.学者识别学者识别

2.学术分析学术分析

3.人才评估人才评估

"同舟云学术"是以全球学者为主线，采集、加工和组织学术论文而形成的新型学术文献查询和分析系统，可以对全球学者进行文献检索和人才价值评估。用户可以通过关注某些学科领域的顶尖人物而持续追踪该领域的学科进展和研究前沿。经过近期的数据扩容，当前同舟云学术共收录了国内外主流学术期刊6万余种，收集的期刊论文及会议论文总量共计约1.5亿篇，并以每天添加12000余篇中外论文的速度递增。我们也可以为用户提供个性化、定制化的学者数据。欢迎来电咨询！咨询电话：010-8811{复制后删除}0370

www.globalauthorid.com

TOP