Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off-Reference-Cited by-同舟云学术

Wafer-scale layer transfer of GaAs and Ge onto Si wafers using patterned epitaxial lift-off

Published:2015-02-12 Issue:3 Volume:54 Page:036505
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Mieda Eiko,Maeda Tatsuro,Miyata Noriyuki,Yasuda Tetsuji,Kurashima Yuichi,Maeda Atsuhiko,Takagi Hideki,Aoki Takeshi,Yamamoto Taketsugu,Ichikawa Osamu,Osada Takenori,Hata Masahiko,Ogawa Arito,Kikuchi Toshiyuki,Kunii Yasuo

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/54/i=3/a=036505/pdf

Reference32 articles.

1. Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance

2. Self-aligned III-V MOSFETs heterointegrated on a 200 mm Si substrate using an industry standard process flow

3. III-V-semiconductor-on-insulator n-channel metal-insulator-semiconductor field-effect transistors with buried Al2O3 layers and sulfur passivation: Reduction in carrier scattering at the bottom interface

4. Ge layer transfer to Si for photovoltaic applications

5. An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling

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