The impact of energy barrier height on border traps in the metal insulator semicondoctor gate stacks on III–V semiconductors-Reference-Cited by-同舟云学术

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The impact of energy barrier height on border traps in the metal insulator semicondoctor gate stacks on III–V semiconductors

Published:2016-05-19 Issue:8S2 Volume:55 Page:08PC01
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Yoshida Shinichi,Taniguchi Satoshi,Minari Hideki,Lin Dennis,Ivanov Tsvetan,Watanabe Heiji,Nakazawa Masashi,Collaert Nadine,Thean Aaron

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/55/i=8S2/a=08PC01/pdf

Reference30 articles.

1. Advanced high-K gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon substrate for low power logic applications

2. Enhancement-mode p-channel GaAs MOSFETs on semi-insulating substrates

3. MOSFET performance scaling: Limitations and future options

4. Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution

5. How can high mobility channel materials boost or degrade performance in advanced CMOS

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A comprehensive investigation of the bias temperature instability associated with charge trapping in In0.7Ga0.3As MOSFETs with various high-κ stacks;Japanese Journal of Applied Physics;2018-09-10

2. The impact of forming gas annealing on the electrical characteristics of sulfur passivated Al2O3/In0.53Ga0.47As (110) metal-oxide-semiconductor capacitors;Applied Physics Letters;2017-04-03

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