Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack-Reference-Cited by-同舟云学术

Simulation-based study of negative-capacitance double-gate tunnel field-effect transistor with ferroelectric gate stack

Published:2016-03-18 Issue:4S Volume:55 Page:04EB08
ISSN:0021-4922
Container-title:Japanese Journal of Applied Physics
language:
Short-container-title:Jpn. J. Appl. Phys.

Author:

Liu Chien,Chen Ping-Guang,Xie Meng-Jie,Liu Shao-Nong,Lee Jun-Wei,Huang Shao-Jia,Liu Sally,Chen Yu-Sheng,Lee Heng-Yuan,Liao Ming-Han,Chen Pang-Shiu,Lee Min-Hung

Publisher

IOP Publishing

Subject

General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering

Link

http://stacks.iop.org/1347-4065/55/i=4S/a=04EB08/pdf

Reference35 articles.

1. Ferroelectric negative capacitance hetero-tunnel field-effect-transistors with internal voltage amplification

2. Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on

3. Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope

4. Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+Layer

5. Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes

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