Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

Abstract

Abstract In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.