Optimization of nanosheet number and width of multi-stacked nanosheet FETs for sub-7-nm node system on chip applications
Author:
Publisher
IOP Publishing
Subject
General Physics and Astronomy,Physics and Astronomy (miscellaneous),General Engineering
Link
http://stacks.iop.org/1347-4065/58/i=SB/a=SBBA12/pdf
Reference32 articles.
1. Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node
2. Fin Shape Impact on FinFET Leakage With Application to Multithreshold and Ultralow-Leakage FinFET Design
3. Process-Induced Variations of 10-nm Node Bulk nFinFETs Considering Middle-of-Line Parasitics
4. Statistical variability study of random dopant fluctuation on gate-all-around inversion-mode silicon nanowire field-effect transistors
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