STI∕LOCOS compatible LDMOS structure in standard CMOS
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el_20030916?crawler=true&mimetype=application/pdf
Reference5 articles.
1. Modeling and characterization of CMOS-compatible high-voltage device structures
2. Effect of surface fields on the breakdown voltage of planar silicon p-n junctions
3. Characteristics of p-channel SOI LDMOS Transistor with Tapered Field Oxides
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2. A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage;Japanese Journal of Applied Physics;2012-04-20
3. A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage;Japanese Journal of Applied Physics;2012-04-01
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5. A 2.4-GHz +25dBm P-1dB linear power amplifier with dynamic bias control in a 65-nm CMOS process;ESSCIRC 2008 - 34th European Solid-State Circuits Conference;2008-09
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