Multi‐valued logic design methodology with double negative differential resistance transistors-Reference-Cited by-同舟云学术

Multi‐valued logic design methodology with double negative differential resistance transistors

Published:2017-10 Issue:10 Volume:12 Page:738-743
ISSN:1750-0443
Container-title:Micro & Nano Letters
language:en
Short-container-title:Micro & Nano Letters

Author:

Ji Yuchao¹,Chang Sheng¹,Wang Hao¹,Huang Qijun¹,He Jin¹,Yi Fan²

Affiliation:

1. Key Laboratory of Acoustic and Photonic Materials and Devices of Ministry of EducationSchool of Physics and TechnologyWuhan UniversityWuhan430072People's Republic of China

2. School of Electronics and Information EngineeringWuhan Donghu UniversityWuhan430212People's Republic of China

Funder

Natural Science Foundation of Hubei Province

China Postdoctoral Science Foundation

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/mnl.2017.0163

Reference21 articles.

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2. Current-mode CMOS multiple-valued logic circuits

3. Low power dissipation MOS ternary logic family

4. VudadhaC.KatragaddaS.PhaneendraP.S.: ‘2:1 Multiplexer based design for ternary logic circuits’.IEEE Asia Pacific Conf. on Postgraduate Research in Microelectronics and Electronics (PrimeAsia) Visakhapatnam 2013 pp.46–51

5. Realization of quaternary logic circuits by n-channel MOS devices

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