2:1 Multiplexer based design for ternary logic circuits
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Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6720586/6731163/06731176.pdf?arnumber=6731176
Cited by 9 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. High-speed low power energy efficient 1- trit multiplier with less number of CNTFETs;Multimedia Tools and Applications;2023-08-14
2. A review on the design of ternary logic circuits*;Chinese Physics B;2021-12-01
3. Ternary logic decoder using independently controlled double-gate Si-NW MOSFETs;Scientific Reports;2021-06-21
4. Comparative Study of CNTFET Implementations of 1-trit Multiplier;2020 32nd International Conference on Microelectronics (ICM);2020-12-14
5. A Half Adder Design Based on Ternary Multiplexers in Carbon Nano-Tube Field Effect Transistor (CNFET) Technology;ECS Journal of Solid State Science and Technology;2020-09-11
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