Current mirror‐based compensation circuit for multi‐row read in‐memory computing-Reference-Cited by-同舟云学术

Current mirror‐based compensation circuit for multi‐row read in‐memory computing

Published:2019-10 Issue:22 Volume:55 Page:1176-1178
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Lin Zhiting¹,Fang Yaqi¹,Peng Chunyu¹,Lu Wenjuan¹,Li Xuan¹,Wu Xiulong¹,Chen Junning¹

Affiliation:

1. School of Electronics and Information EngineeringAnhui UniversityHefei230601People's Republic of China

Funder

National Natural Science Foundation of China

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2019.2415

Reference13 articles.

1. Computational RAM: implementing processors in memory;Elliott D.G.;Design Test Comput.,1999

2. Smart Memories: A Modular Reconfigurable Architecture

3. Kang M. Yamaoka M. Morimoto M.et. al. :‘A 481pJ/decision 3.4M decision/s Multifunctional Deep In‐memory Inference Processor using Standard 6 T SRAM Array’ arXiv Preprint 2016 https://arxiv.org/abs/1610.07501

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