Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Abstract

To increase the throughput of computing-in-memory (CIM) designs, multi-row read methods have been adopted to increase computation in the analog region. However, the nonlinearity created by doing so degrades the precision of the results obtained. The results of CIM computation need to be precise in order for CIM designs to be used in machine learning circumstances involving complex algorithms and big data sets. In this study, a low computing leakage, wide-swing output compensation circuit is proposed for linearity improvement in such circumstances. The proposed compensation circuit is composed of a current competition circuit (as dynamic feedback of the bitline discharge current), a current mirror (to separate the result capacitor and provide charge current), and an additional pull-down circuit (for better precision in high voltage results). Measurements show that by applying our method, an almost full-swing output with 51.2% nonlinearity decrement compared with no compensation can be achieved. Power consumption is reduced by 36% per round on average and the computing leakage current, after wordlines are deactivated for 1 ns, is reduced to 55% of that when using conventional methods. A figure of merit (FOM) is proposed for analog computing module evaluation, presenting a comprehensive indicator for the computation precision of such designs.