Design of Neural Network Accelerator Based on In-Memory Computing Theory

Author:

Wu Jin1,Zhao Bo1,Wen Heng1,Zhao Qianchao1

Affiliation:

1. Xi’an University of Posts and Telecommunication,Dept. School of Electronic Engineering,Xi’an,China

Publisher

IEEE

Reference12 articles.

1. Embedded 1-Mb ReRAM-Based Computing-in- Memory Macro With Multibit Input and Weight for CNN-Based AI Edge Processors

2. Hardware and software co-optimization for mitigating the initialization failure of the ReRAM based cross-bar array[J];kim;ACM Journal on Emerging Technologies in Computing Systems,2020

3. A Logic-Compatible eDRAM compute-in-memory with embedded ADCs for processing neural networks[J];yu;IEEE Transactions on Circuits and Systems I Regular Papers,2020

4. Current mirror‐based compensation circuit for multi‐row read in‐memory computing

5. In-memory computing to break the memory wall*

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