Parallel architecture of power‐of‐two multipliers for FPGAs-Reference-Cited by-同舟云学术

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Parallel architecture of power‐of‐two multipliers for FPGAs

Published:2020-02-28 Issue:3 Volume:14 Page:381-389
ISSN:1751-858X
Container-title:IET Circuits, Devices & Systems
language:en
Short-container-title:IET Circuits, Devices & Systems

Author:

Perri Stefania¹,Spagnolo Fanny²,Frustaci Fabio²,Corsonello Pasquale²

Affiliation:

1. Department of Mechanical, Energy and Management Engineering (DIMEG)University of Calabria87036Arcavacata di RendeItaly

2. Department of Informatics, ModelingElectronics and System Engineering (DIMES), University of Calabria87036Arcavacata di RendeItaly

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cds.2019.0246

Reference33 articles.

1. ‘Zynq‐7000 SoC technical reference manual UG585 (v1.12.2)’ July2018 Available at:www.xilinx.com accessed 27 May 2019

2. ‘Zynq ultrascake + device technical reference manual UG1085 (v. 1.8)’ August2018 Available at:www.xilinx.com accessed 27 May 2019

3. ‘Stratix 10 GX/SX device overview’ Available at:www.intel.com accessed 27 May 2019

4. ‘Arria 5/10 SoC FPGAs’ Available at:www.intel.com accessed 27 May 2019

5. Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms

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