A Novel Design of High-Performance Hybrid Multiplier

Abstract

In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.