A Fresh Design of Power Effective Adapted Vedic Multiplier for Modern Digital Signal Processors
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electrical and Electronic Engineering,Computer Science Applications
Link
https://link.springer.com/content/pdf/10.1007/s11277-021-09407-x.pdf
Reference25 articles.
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2. Vijeyakumar, K. N., Sumathy, V., & Elango, S. (2014). VLSI implementation of area-efficient truncated modified booth multiplier for signal processing applications. Arabian Journal for Science and Engineering, 39(11), 7795–7806.
3. Gavaskar, K., & Ragupathy U. S. (2014). An efficient design and comparative analysis of low power memory cell structures. In 2014 International Conference on Green Computing Communication and Electrical Engineering (ICGCCEE). IEEE.
4. Sakellariou, P., & Paliouras, V. (2016). Application-specific low-power multipliers. IEEE Transactions on Computers, 65(10), 2973–2985.
5. Gavaskar, K., Ragupathy, U. S., & Malini, V. (2019). Design of novel SRAM cell using hybrid VLSI techniques for low leakage and high speed in embedded memories. Wireless Personal Communications, 108(4), 2311–2339.
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