Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors-Reference-Cited by-同舟云学术

Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors

Published:2022-09-10 Issue:2 Volume:128 Page:1417-1435
ISSN:0929-6212
Container-title:Wireless Personal Communications
language:en
Short-container-title:Wireless Pers Commun

Author:

Gavaskar K.^ORCID,Malathi D.,Ravivarma G.,Priyatharshan P. S.,Rajeshwari S.,Sanjay B.

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

https://link.springer.com/content/pdf/10.1007/s11277-022-10006-7.pdf

Reference32 articles.

1. Guarnieri, M. (2016). The unreasonable accuracy of Moore’s Law [Historical]. IEEE Industrial Electronics Magazine, 10(1), 40–43.

2. Alioto, M. (2012). Ultra-low power VLSI circuit design demystified and explained: A tutorial. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(1), 3–29.

3. Venkatachalam, S., & Ko, S. B. (2017). Design of power and area efficient approximate multipliers. IEEE Transactions on Very Large Scale Integration VLSI Systems, 25(5), 1782–1786.

4. Kim, S., Kang, Y., Baek, S., Choi, Y., & Kang, S. (2021). Low-power ternary multiplication using approximate computing. IEEE Transactions on Circuits and Systems II: Express Briefs, 68(8), 2947–2951.

5. Han, L., & Ko, S. B. (2012). High-speed parallel decimal multiplication with redundant internal encodings. IEEE Transactions on Computers, 62(5), 956–968.

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