Internal write‐back and read‐before‐write schemes to eliminate the disturbance to the half‐selected cells in SRAMs

Author:

Pasandi Ghasem1ORCID,Pedram Massoud1

Affiliation:

1. Department of Electrical Engineering‐SystemsUniversity of Southern CaliforniaLos AngelesCA90089USA

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Cited by 20 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A FinFET-based low-power, stable 8T SRAM cell with high yield;AEU - International Journal of Electronics and Communications;2024-02

2. A low-power SRAM design with enhanced stability and ION/IOFF ratio in FinFET technology for wearable device applications;International Journal of Electronics;2023-07-25

3. High-Stability and High-Speed 11T CNTFET SRAM Cell for MIMO Applications;Journal of Circuits, Systems and Computers;2023-06-12

4. Energy-Efficient Single-Ended Read/Write 10T Near-Threshold SRAM;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-05

5. Review of 6T SRAM for Embedded Memory Applications;Indian Journal of VLSI Design;2023-03-30

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