Approach of genetic algorithm for power‐aware testing of 3D IC-Reference-Cited by-同舟云学术

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Approach of genetic algorithm for power‐aware testing of 3D IC

Published:2019-07-16 Issue:5 Volume:13 Page:383-396
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Kaibartta Tanusree¹,Giri Chandan²,Rahaman Hafizur²,Das Debesh Kumar³

Affiliation:

1. Department of Computer Science and EngineeringIndian Institute of TechnologyDhanbad826004JharkhandIndia

2. Department of Information TechnologyIndian Institute of Engineering Science and TechnologyHowrah711103West BengalIndia

3. Department of Computer Science and EngineeringJadavpur UniversityKolkata700032West BengalIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2018.5079

Reference41 articles.

1. Klumpp A. Ramm P. Wieland R.: ‘3D‐integration of silicon devices: a key technology for sophisticated products’.Proc. Design Automation Test Europe Conf. Exhibition (DATE) Dresden Germany 2010 pp.1678–1683

2. Modeling and layout optimization for tapered TSVs;Lu T.;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2015

3. TSV-Based 3-D ICs: Design Methods and Tools

4. Semiconductor Industry Association (SIA): In:International Technology Roadmap for Semiconductors (ITRS) 2013

5. Pawlowski J.T.: ‘Hybrid memory cube (HMC)’.Proc. IEEE Hot Chips 23 Symp. (HCS) Stanford CA USA 2011 vol. 23 pp.1–24

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1. A reconfigurable test method based on LFSR for 3D stacking integrated circuits;Integration;2022-11

2. Fast algorithms for test optimization of core based 3D SoC;Integration;2021-03

3. Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs;Journal of Electronic Testing;2020-04

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