Co-Optimization of Test Wrapper Length and TSV for TSV Based 3D SOCs

Author:

Kaibartta TanusreeORCID,Biswas G. P.,Das Debesh Kumar

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Reference25 articles.

1. Cheng Y, Zhang L, Han Y, Liu J, Li X (2011) Wrapper chain design for testing TSVs minimization in circuit-partitioned 3D SoC. In: Proc of IEEE Asian test symposium (ATS), pp 181–186

2. Garey M R, Johnson D S (1979) Computers and Intractability - A guide to the theory of NP-completeness W.H. Freeman and Company, San Francisco

3. Goel SK, Marinissen EJ (2003) SOC Test architecture design for efficient utilization of test bandwidth. ACM Trans Des Autom Electron Syst 8:399–429

4. Harutal T, Nakajima T, Hashizume J et al (2017) 4.6 a 1/2.3in 20Mpixel 3-layer stacked CMOS image sensor with DRAM. In: Proc of IEEE international solid-state circuits conference (ISSCC), San Francisco, CA, pp 76–77

5. Iyengar V, Chakrabarty K, Marinissen E J (2002) Test wrapper and test access mechanism co-optimization for System-on-Chip. Journal of Electronic Testing: Theory and Applications (JETTA) 18:213–230

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