Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network-Reference-Cited by-同舟云学术

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Power‐aware floorplanning‐based power through‐silicon‐via technology and bump minimisation for three‐dimensional power delivery network

Published:2014-09 Issue:5 Volume:8 Page:210-218
ISSN:1751-8601
Container-title:IET Computers & Digital Techniques
language:en
Short-container-title:IET Computers & Digital Techniques

Author:

Jang Cheoljon¹,Kim Jaehwan¹,Chong Jongwha¹

Affiliation:

1. Department of Electronics Computer EngineeringHanyang UniversitySeoul133‐791Korea

Funder

Ministry of Science, ICT and Future Planning

IC Design Education Center

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-cdt.2013.0118

Reference29 articles.

1. Cramming more components onto integrated circuits;Moore G.E.;IEEE Solid‐State Circuits Newsl.,1998

2. Integration schemes and enabling technologies for three-dimensional integrated circuits

3. Through-Silicon Via Planning in 3-D Floorplanning

4. TSV Redundancy: Architecture and Design Issues in 3-D IC

5. Jain A. Jones R.E. Chatterjee R. Pozder S. Huang Z.: ‘Thermal modeling and design of 3D integrated circuits’.Eleventh Intersociety Conf. Thermal and Thermomechanical Phenomena in Electronic Systems 2008 (ITHERM 2008) May2008 pp.1139–1145

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. WITHDRAWN: A novel power aware placement and adaptive radix tree based clock tree synthesis for 3D-integrated circuits;Microprocessors and Microsystems;2020-11

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