Experimentally verified drain‐current model for variable barrier transistor-Reference-Cited by-同舟云学术

Experimentally verified drain‐current model for variable barrier transistor

Published:2015-08 Issue:17 Volume:51 Page:1364-1366
ISSN:0013-5194
Container-title:Electronics Letters
language:en
Short-container-title:Electron. lett.

Author:

Moldovan O.¹,Lime F.¹,Barraud S.²,Smaani B.³,Latreche S.³,Iñiguez B.¹

Affiliation:

1. Department of Electronic, Electric & Automatic, EngineeringUnivRovira & VirgiliTarragona43007Spain

2. MinatecCEA LETIGrenobleF‐38054France

3. Département d'ElectroniqueUniversité Constantine 1, Faculté des Sciences de la Technologie, Laboratoire Hyperfréquences et Semi‐conducteurs (LHS)ConstantineAlgérie

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering

Link

https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.1475

Reference11 articles.

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2. Physics of gate modulated resonant tunneling (RT)‐FETs: Multi‐barrier MOSFET for steep slope;Afzalian A.;Solid‐State Electron.,2011

3. Unified compact model for the ballistic quantum wire and quantum well metal-oxide-semiconductor field-effect-transistor

4. Ballistic metal‐oxide‐semiconductor field effect transistor;Natori K.;J. Appl. Phys.,1994

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