Analogue/RF performance attributes of underlap tunnel field effect transistor for low power applications
Author:
Affiliation:
1. Nanoscale devices VLSI circuit and system design labIndian Institute of TechnologyIndoreIndia
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/el.2015.3797
Reference6 articles.
1. Investigation of parasitic effects and design optimization in silicon nanowire MOSFETs for RF applications;Zhuge J.;IEEE Electron Devices,2008
2. Analog performance of double gate SOI transistors
3. Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric
4. Tunnel field‐effect transistor without gate–drain overlap;Verhulst A.S.;Appl. Phys. Lett.,2007
5. Simulation study on effect of drain underlap in gate‐all‐around tunneling field‐effect transistors;Lee J.S.;Current Appl. Phys.,2013
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