Performance Analysis of Vertically Stacked Nanosheet Tunnel Field Effect Transistor with Ideal Subthreshold Swing
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
https://link.springer.com/content/pdf/10.1007/s12633-021-01302-1.pdf
Reference34 articles.
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2. Barraud S, Lapras V, Previtali B, Samson MP, Lacord J, Martinie S, Jaud MA, Athanasiou S, Triozon F, Rozeau O, Hartmann JM, Vizioz C, Comboroure C, Andrieu F, Barbé JC, Vinet M, Ernst T (2017) Performance and design considerations for gate-all-around stacked-NanoWires FETs. IEEE International Electron Devices Meeting (IEDM). doi: https://doi.org/10.1109/IEDM.2017.8268473
3. Yakimets D, Bardon MG, Jang D, Schuddinck P, Sherazi Y, Weckx P, Miyaguchi K, Parvais B, Raghavan P, Spessot A, Verkest D, Mocuta A (2017) Power-aware FinFET and lateral nanosheet FET targeting for 3nm CMOS technology. IEEE international Electron devices meeting (IEDM), San Francisco. https://doi.org/10.1109/IEDM.2017.8268429
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