Ultra‐low leakage SRAM design with sub‐32 nm tunnel FETs for low standby power applications

Author:

Makosiej Adam1,Gupta Navneet2,Vakul Naga2,Vladimirescu Andrei2,Cotofana Sorin3,Mahapatra Santanu4,Amara Amara2,Anghel Costin2

Affiliation:

1. Commissariat a l'Energie Atomique CEA‐LETIGrenobleFrance

2. Institut superieur d'electronique de ParisParisFrance

3. Computer Engineering Laboratory Faculty of Electrical EngineeringMathematics and Computer ScienceDelft University of TechnologyDelftNetherlands

4. Indian Institute of ScienceBangaloreIndia

Publisher

Institution of Engineering and Technology (IET)

Subject

Condensed Matter Physics,General Materials Science,Biomedical Engineering,Bioengineering

Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Investigation of Cylindrical Channel Gate All Around InGaAs/InP Heterojunction Heterodielectric Tunnel FETs;Silicon;2020-09-13

2. Design of an AAM 6T-SRAM Cell Variation in the Supply Voltage for Low Power Dissipation and High Speed Applications using 20nm Finfet Technology;2020 International Conference on Inventive Computation Technologies (ICICT);2020-02

3. Low-Power High-Performance Tunnel FET With Analysis for IoT Applications;Handbook of Research on the Internet of Things Applications in Robotics and Automation;2020

4. An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications;Analog Integrated Circuits and Signal Processing;2019-11-22

5. Robust TFET SRAM cell for ultra-low power IoT applications;AEU - International Journal of Electronics and Communications;2018-05

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