An advanced adiabatic logic using Gate Overlap Tunnel FET (GOTFET) devices for ultra-low power VLSI sensor applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-019-01561-4.pdf
Reference31 articles.
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2. Thapliyal, H., Varun, T. S. S., & Kumar, S. D. (2017). In 2017 IEEE Computer society annual symposium on VLSI (ISVLSI) (pp. 621–626). https://doi.org/10.1109/ISVLSI.2017.115
3. Kao, K., Verhulst, A. S., Vandenberghe, W. G., Soree, B., Magnus, W., Leonelli, D., et al. (2012). Optimization of gate-on-source-only tunnel FETs with counter-doped pockets. IEEE Transactions on Electron Devices, 59(8), 2070. https://doi.org/10.1109/TED.2012.2200489.
4. Chander, S., Bhowmick, B., & Baishya, S. (2015). Heterojunction fully depleted SOI-TFET with oxide/source overlap. Superlattices and Microstructures, 86, 43. https://doi.org/10.1016/j.spmi.2015.07.030.
5. Schulte-Braucks, C., Pandey, R., Sajjad, R. N., Barth, M., Ghosh, R. K., Grisafe, B., et al. (2017). Fabrication, characterization, and analysis of Ge/GeSn heterojunction p-type tunnel transistors. IEEE Transactions on Electron Devices, 64(10), 4354. https://doi.org/10.1109/TED.2017.2742957.
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